1. Technical Field
The present disclosure relates to the production of an integrated circuit on a semiconductor wafer, comprising a data buffer circuit connected to a contact pad.
The present disclosure in particular relates to the production of a data buffer circuit that is compatible with both the “High Speed” USB (Universal Serial Bus) specification and the “Full Speed” USB specification.
2. Description of the Related Art
FIG. 1 shows an integrated circuit IC comprising a conventional data buffer circuit CBUF and a contact pad IOP (“I/O Pad”). The buffer circuit CBUF comprises two transistors T1, T2 of MOS (Metal Oxide Semiconductor) technology. The transistor T1 is of the type PMOS and the transistor T2 is of the type NMOS. The transistor T1 receives on its source (S) a voltage Vcc. The drain (D) of transistor T1 is connected to the drain (D) of transistor T2, the source of which is linked to ground (GND). The drains (D) of the transistors T1, T2 are connected to the pad IOP. The gate (G) of transistor T1 receives a data signal DT1 (i.e., a data carrying signal) and the gate of transistor T2 receives a data signal DT2, the signals DT1, DT2 being supplied by a circuit CT.
Table 1 below describes the functioning of the buffer circuit CBUF. The buffer circuit functions as an inverter and supplies to the pad IOP a signal DOUT that is the inverse of signals DT1, DT2. The signals DT1, DT2 are identical during a data transmission, and can therefore be considered as a single and same data signal. Outside of the data transmission periods, they are respectively set at 1 and 0 to place the buffer circuit in a high impedance state (transistors T1, T2 non-conducting).
TABLE 1DT1 (T1)DT2 (T2)DOUT0 (GND)0 (GND)1 (Vcc)1 (Vcc)1 (Vcc)0 (GND)1 (Vcc)0 (GND)HZ (high impedance)
The electric characteristics of the buffer circuit CBUF are, in practice, highly dependent upon those of the transistors T1, T2 of which it is composed. During the conception of the integrated circuit, a specification list defines the desired performances in terms of the withstand voltage (maximum continuous voltage that the buffer circuit should be able to withstand), of the pass band (maximum frequency of data signals that the buffer circuit should be able to transmit), and of the resistance to electrostatic discharges (maximum discharge voltage that the buffer circuit should be able to withstand).
To make low-cost integrated circuits, circuit designers try to design such a buffer circuit with the transistors at their disposal, that is, the transistors used for the rest of the integrated circuit. In the case of an integrated circuit comprising a non-volatile memory, for example an electrically erasable and programmable memory of the type EEPROM or Flash-EEPROM, designers have at their disposal two types of transistors:                high voltage transistors with a thick oxide, used to produce the non-volatile memory and able to withstand a voltage on the order of 10 V (for example a voltage for programming or erasing), and        transistors with a thin gate oxide (called “logic” transistors, i.e., allowing logic circuitry to be produced).        
However, the logic transistors have a broad pass band but a low withstand voltage, and the high voltage transistors have a small pass band: if the frequency of the signals DT1, DT2 increases, they are not able to “follow” the signal variations and transmit the data (they switch too slowly from the conducting state to the non-conducting state and vice-versa).
Thus, it may be that conventional transistors of an integrated circuit do not allow a buffer circuit offering the desired performances in terms of withstand voltage and of pass band to be produced. The designers must therefore provide specific transistors, causing an increase of the cost price of the integrated circuit because the addition of a third type of transistor requires the provision of diverse additional steps in the fabrication process of the integrated circuit.
The USB standard specifications are a typical example of a specification list that can be problematic. It is known to produce buffer circuits able to meet the “Full Speed” USB specification by using conventional high voltage transistors, because the “Full Speed” USB specification requires a fairly low data transfer frequency, on the order of 12 MHz (that is, 12 Mb/s). However, the “High Speed” USB specification requires a data transfer frequency of 480 MHz (that is, 480 Mbit/s) with differential data signals D+, D− that can be between 400 and 800 mV (that is a 400 mV voltage differential).
More particularly, the differential signals D+, D− transmitted on a USB bus have voltage levels of 0.0 to 0.3 V for the low level (logic 0) and from 2.8 to 3.6 V for the high level (logic 1) in “Full Speed” (FS) mode. In “High Speed” (HS) mode, these signals vary from −10 to +10 mV for the low level and from 360 to 440 mV for the high level.
The “High Speed” specification is therefore more restrictive than the “Full Speed” specification in terms of pass band, but less restrictive in terms of withstand voltage because the data are carried by lower voltages. Nevertheless, a USB buffer circuit provided to emit signals in “High Speed” mode must be able to resist the maximum voltage of 3.6 V required by the “Full Speed” specifications because a data transmission in “High Speed” mode must first be negotiated in “Full Speed” mode before it is switched into the “High Speed” mode. Conventional high voltage transistors can resist such a voltage, but do not allow a buffer circuit in conformance with the USB “High Speed” specifications to be produced because the pass band is too small.